China Sic Coated Wafer Boats Manufacturers, Suppliers, Factory

Chemical vapor deposition CVD refers to the introduction of two or more gaseous raw materials into a reaction chamber under vacuum and high temperature conditions, where the gaseous raw materials react with each other to form a new material, which is deposited on the wafer surface.

Compared with the PVT method, the liquid phase method for growing SiC has the following advantages:

Quartz (SiO₂) material is very similar to glass at first glance, but the special thing is that the general glass is made up of many components (such as quartz sand, borax, boric acid, barite, barium carbonate, limestone, feldspar, soda ash, etc.), while the quartz contains only SiO₂ components, and the microstructure of its silicon dioxide tetrahedral structural units composed of a simple network.

In traditional silicon power device fabrication, high-temperature diffusion and ion implantation stand as the primary methods for dopant control, each with its advantages and disadvantages. Typically, high-temperature diffusion is characterized by its simplicity, cost-effectiveness, isotropic dopant distribution profiles, and lower introduction of lattice damage. Conversely, ion implantation, though complex and costly, enables precise independent control over dopant concentration and depth but introduces a significant number of point defects and extended defects into the substrate.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

To achieve the high-quality requirements of IC chip circuit processes with line widths smaller than 0.13μm to 28nm for 300mm diameter silicon polishing wafers, it is essential to minimize contamination from impurities, such as metal ions, on the wafer's surface.