China robotic arms for manufacturing Manufacturers, Suppliers, Factory

In the high voltage field, particularly for high-voltage devices above 20,000V, the SiC epitaxial technology still faces several challenges. One of the main difficulties is achieving high uniformity, thickness, and doping concentration in the epitaxial layer. For the fabrication of such high-voltage devices, a 200um thick silicon carbide epitaxial wafer with excellent uniformity and concentration is required.

Silicon Carbide generally uses the PVT method, with a temperature of more than 2000 degrees, a long processing cycle, and low output, so the cost of Silicon Carbide substrates is very high.

Currently, many semiconductor devices employ mesa device structures, which are predominantly created through two types of etching: wet etching and dry etching. While the simple and rapid wet etching plays a significant role in semiconductor device fabrication, it has inherent drawbacks such as isotropic etching and poor uniformity, which result in limited control when transferring small-sized patterns. Dry etching, however, with its high anisotropy, good uniformity, and repeatability, has become prominent in semiconductor device fabrication processes. The term “dry etching” broadly refers to any non-wet etching technology used for removing surface materials and transferring micro and nano patterns, including laser etching, plasma etching, and chemical vapor etching. The dry etching discussed in this text specifically pertains to the narrow application of processes using plasma discharge—either physical or chemical—to modify material surfaces.

Silicon carbide substrate is a compound semiconductor single crystal material composed of two elements, carbon and silicon. It has the characteristics of large bandgap, high thermal conductivity, high critical breakdown field strength, and high electron saturation drift rate.

​As the world searches for new opportunities in the semiconductor field, Gallium Nitride (GaN) continues to stand out as a potential candidate for future power and RF applications. However, despite its numerous benefits, GaN faces a significant challenge: the absence of P-type products. Why is GaN hailed as the next major semiconductor material, why is the lack of P-type GaN devices a critical drawback, and what does this mean for future designs?

The wafer notch is a V-shaped or U-shaped groove on the edge of a semiconductor wafer. Far from being a defect incurred during the manufacturing process, it is the critical structural marker that was intentionally designed, whose core function lies in enabling precise positioning and orientation identification of the wafer. Wafer flat was used as the orientation marking in the early stages of wafer technology development. However, as wafer sizes gradually increased, the flat-edge design occupied more effective area, thus being gradually replaced by the more compact notch.