China Epitaxial Tray Manufacturers, Suppliers, Factory

Within the silicon carbide (SiC) industry chain, substrate suppliers hold significant leverage, primarily due to value distribution. SiC substrates account for 47% of the total value, followed by epitaxial layers at 23%, while device design and manufacturing constitute the remaining 30%. This inverted value chain stems from the high technological barriers inherent to substrate and epitaxial layer production. Three major challenges plague SiC substrate growth: stringent growth conditions, slow growth rates, and demanding crystallographic requirements. These complexities contribute to increased processing difficulty, ultimately resulting in low product yields and high costs. Furthermore, the epitaxial layer’s thickness and doping concentration are critical parameters directly impacting the final device performance.

Silicon carbide (SiC) crystal growth furnaces are the cornerstone of SiC wafer production. While sharing similarities with traditional silicon crystal growth furnaces, SiC furnaces face unique challenges due to the material’s extreme growth conditions and complex defect formation mechanisms. These challenges can be broadly categorized into two areas: crystal growth and epitaxial growth.

Carbon-based materials such as graphite, carbon fibers, and carbon/carbon (C/C) composites are known for their high specific strength, high specific modulus, and excellent thermal properties, making them suitable for a wide range of high-temperature applications. These materials are widely utilized in aerospace, chemical engineering, and energy storage. However, their susceptibility to oxidation and corrosion in high-temperature environments, along with poor scratch resistance, restricts their further application.

The wafer notch is a V-shaped or U-shaped groove on the edge of a semiconductor wafer. Far from being a defect incurred during the manufacturing process, it is the critical structural marker that was intentionally designed, whose core function lies in enabling precise positioning and orientation identification of the wafer. Wafer flat was used as the orientation marking in the early stages of wafer technology development. However, as wafer sizes gradually increased, the flat-edge design occupied more effective area, thus being gradually replaced by the more compact notch.

SOI(Silicon-On-Insulator) substrate is structure in which a silicon oxide (SiO2) insulating layer is introduced between a top silicon layer and a silicon substrate, and integrated circuits are fabricated on the top silicon thin layer. This technology of using SOI materials to manufacture integrated circuits is called SOI technology.