China Epi Process Semiconductor Manufacturers, Suppliers, Factory

SiC MOSFETs are transistors that offer high power density, improved efficiency, and low failure rates at high temperatures. These advantages of SiC MOSFETs bring numerous benefits to electric vehicles (EVs), including longer driving range, faster charging, and potentially lower cost battery electric vehicles (BEVs). Over the past five years, SiC MOSFETs have been widely used in the power electronics of EVs in vehicles from OEMs such as Tesla and Hyundai. In fact, SiC inverters accounted for 28% of the BEV market in 2023.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

The silicon carbide industry involves a chain of processes that include substrate creation, epitaxial growth, device design, device manufacturing, packaging, and testing. In general, silicon carbide is created as ingots, which are then sliced, ground, and polished to produce a silicon carbide substrate.

Gallium Nitride (GaN) is an important material in semiconductor technology, known for its exceptional electronic and optical properties. GaN, as a wide-bandgap semiconductor, has a bandgap energy of approximately 3.4 eV, making it ideal for high-power and high-frequency applications.

In semiconductor manufacturing, atomic-level flatness is usually used to describe the global flatness of the wafer, with the unit of nanometers (nm).