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Semiconductor materials can be divided into three generations according to the time sequence. The first generation of germanium, silicon and other common monomaterials, which is characterised by convenient switching, generally used in integrated circuits. The second generation of gallium arsenide, indium phosphide and other compound semiconductors, mainly used for light-emitting and communication materials.

We know that further epitaxial layers need to be built on top of some wafer substrates for device fabrication, typically LED light-emitting devices, which require GaAs epitaxial layers on top of silicon substrates; SiC epitaxial layers are grown on top of conductive SiC substrates for building devices such as SBDs, MOSFETs, etc. for high voltage, high current and other power applications; GaN epitaxial layers are built on top of semi-insulating SiC substrates for building HEMTs and other RF applications.

The growth of GaN epitaxy on GaN substrate presents a unique challenge, despite the material’s superior properties when compared to silicon. GaN epitaxy offers significant advantages in terms of band gap width, thermal conductivity, and breakdown electric field over silicon-based materials. This makes the adoption of GaN as the backbone for the third generation of semiconductors, which provide enhanced cooling, lower conduction loss, and improved performance under high temperatures and frequencies, a promising and crucial advancement for the photonic and micro-electronic industries.

AlN, as third-generation semiconductor material, is not only an important blue light and ultraviolet light material, but also an important packaging, dielectric isolation and insulation material for electronic devices and integrated circuits, especially suitable for high-temperature and high-power devices. In addition, AlN and GaN have a good thermal match and chemical compatibility, AlN used as GaN epitaxial substrate, can significantly reduce the defect density in GaN devices, improve device performance.

To achieve the high-quality requirements of IC chip circuit processes with line widths smaller than 0.13μm to 28nm for 300mm diameter silicon polishing wafers, it is essential to minimize contamination from impurities, such as metal ions, on the wafer's surface.

The liquid phase method is closer to the thermodynamic equilibrium conditions and is able to grow SiC crystals with better quality.